The present invention relates to insulated gate field effect transistors and more specifically to an improved high speed, high current gain insulated gate field effect transistor.
To increase the current gain of an insulated gate field effect transistor, it is well known to increase the channel width to length (W/L) ratio. A typical example is illustrated in U.S. Pat. No. 3,586,930 to Das et al. wherein diffused source and drain regions extend interdigitated toward each other from opposing diffused base regions. Contacts are made to the diffused base regions. The metal gate includes U-shaped loops connected to a base portion. Thus in effect, a single field effect transistor is made up of a plurality of field effect transistors connected in parallel. By using diffused source and drain fingers extending from a base, the metal to metal spacing restriction of the source and drain electrodes which hinders large width to length ratios, is eliminated. It should be noted that this structure increases switching delay time since the resistance of the source and drain structures is increased since the current must travel from the base portion through many squares of diffusion to the individual fingers.
Another example to alleviate the metal to metal spacing limitation is illustrated in U.S. Pat. No. 3,484,865 to Nienhuis wherein the contact to either the source or drain region is made on the opposite planar surface than the gate and the other source or drain connections. A very complicated structure having interdigitated source and gate electrodes with a crossing drain electrode is illustrated in U.S. Pat. No. 4,015,278 to Fukuta.
Although the prior art has increased the width to length ratio of the channel by using a plurality of source and drain regions connected in parallel, the resulting increased resistance of these regions because of the contact and interconnect schemes severely reduces the speed of the device. Thus there exists a need for a high speed, high current gain insulated gate field effect transistor.